1. Field of the Invention
The present invention relates to a semiconductor memory device which is selectively supplied with different power source voltages.
2. Description of the Related Art
As known, in a nonvolatile memory device used in a write mode to write data into memory cells, a high voltage is applied to a decode line coupled with the gate or drain of the memory cell to which data is to be loaded.
FIG. 1 shows a circuit diagram of a major part of a conventional EEPROM (electrically erasable and programmable ROM) known as a nonvolatile memory device. The operation of the EEPROM wherein a high voltage is applied to the decode line, will be described. In response to a chip enable signal CE supplied to a control circuit or controller 51, the memory system is driven to be in a operation mode. During the operation mode, data is written into the memory cell by a write signal WR supplied to the controller 51. Specifically, an address signal AD is decoded by a decoder 52, so that one of the decode lines 53 is selected and energized to be set in logic "1" level. The potential of the logic "1" level is applied, through a selected cell row 55 (selected cell row) connected to the selected decode line 53 in a memory matrix 54, to a charge pump circuit 56 connected to the selected cell row. As a result, a high voltage generated by a high voltage generator 57 is supplied to the decode line 53, through the charge pump 56.
The charge pump 56 and the high voltage generator 57 are respectively driven by clock signals CK1 and CK2.
FIG. 2 shows a detailed circuit diagram of the charge pump circuit 56 in the memory system of FIG. 1. In the charge pump 56, the gate of an n-channel MOS transistor 61 is connected to the decode line 53. A high voltage Vpp generated by the high voltage generator 57 is applied to the drain of the transistor 61. The source-drain path of a n-channel MOS transistor 62 is inserted between the gate and the source of the transistor 61. The gate of the transistor 62 is connected to its drain. Accordingly, the clock signal CK1 is supplied through a capacitor 63 to the charge pump. During the operation mode that the chip enable signal CE is being generated, the clock signal CK1 is constantly supplied at predetermined periods.
In the charge pump 56 thus arranged, the decoder 52 applies a voltage of 5 V, for example, to a selected decoder line 53. The voltage is applied through the selected cell row 55 to the gate of the transistor 61 of the charge pump 56 connected to the cell row. In response to the voltage, the transistor 61 is turned on, so that with the high voltage Vpp applied to its drain, a voltage (5V) nearly equal to the gate voltage of the transistor 61 is applied to the gate and the drain of the transistor 62 and a first end of the capacitor 63. The voltage is boosted through the pumping operation by the clock signal CK1 applied to the second end of the capacitor 63 and swinging between 0V and 5V. The boosted voltage is applied to the gate and the drain of the transistor 62, and the first end of the capacitor 63. The boosted voltage is also supplied to the gate of the transistor 61 through the transistor 62. The above sequence of operations is repeated, and finally a voltage, which is the sum of the output voltage Vpp of the high voltage generator 57 and the boosted voltage ".alpha." by the pumping of the clock CK1, is applied to the gate of the transistor 61, i.e., the selected decode line 53. In this way, the voltage of a satisfactorily large amplitude is applied to the cell row 54 coupled with the selected decode line 53.
The non-selected decode line 53 receives 0V from the decoder 52, so that the transistor 61 of the charge pump 56 coupled with the non-selected decode line 53 is turned off.
The clock signal CK1 is applied to all of the charge pumps 56 irrespective of their connections to the selected line or non-selected decode line. Accordingly, in the charge pumps coupled with the non-selected decode lines, the pumping operation is performed through the capacitor 63 when the level of the clock signal changes, so that a minute voltage is applied to the gate and the drain of the transistor 62. Further, the minute voltage is applied to the gate of the transistor 61 through the transistor 62. Finally, the transistor 61 is turned on and the high voltage Vpp generated by the high voltage generator 57 is applied to the drain of the transistor 62 and the capacitor 63. Thus, even for the nonselected decode line, a current path is inevitably formed, which is through the high voltage generator 57, the transistors 61 and 62 of the charge pump 56, and the non-selected decode line 53. As a result, the high voltage generated by the high voltage generator 57 drops, and there is the possibility that the high voltage Vpp, that is supplied to the selected decoder line, is unsatisfactorily high. The high voltage generator 57 is formed on the integrated circuit, and its current capacity is small. Therefore, when the current path is formed, it cannot generate a high voltage.
The charge pump 56 shown in FIG. 2 is constructed with n-channel MOS transistors. Generally, the n-channel MOS transistor is turned on when the voltage Vgs between the gate and the source exceeds the threshold voltage Vth. In the charge pump circuit 56, the drain voltage of the transistor 61 is Vpp and hence high. The effective threshold voltage V of the transistor 61 is (Vth+.beta.), which is higher than the theoretical value due to the back-gate effect. Therefore, the voltage to turn on the n-channel MOS transistor is increased by the back-gate voltage .beta., and is given by the following relation EQU Vgs&gt;Vth+.beta.
where
Vth: threshold voltage of the transistor 61, PA1 .beta.: back-gate voltage due to the back-gate effect.
Thus, as the voltage Vpp is higher, it is more difficult to turn on the transistor 61. To avoid this, the charge pump should be operated at a low voltage. In this case, the pumping operation necessarily progresses at a low voltage. Accordingly, the voltage required when the clock signal CK1 charges the capacitor 63 is low, resulting in a smaller increase of the gate - source voltage Vgs of the transistor 62. The result is that the transistor fails to turn on and the selected decode line 53 is saturated at a certain voltage, and a satisfactorily high voltage cannot be applied to the selected decode line 53.
As described above, the conventional semiconductor memory device using the charge pump circuit suffers from a great current loss, because the pumping operation of the charge pump causes the current from high voltage generator to flow to the non-selected decode line. Further, when the memory system is operated at a low voltage, the pumping operation of the charge pump is not perfect. Accordingly, the high voltage, which is generated by the high voltage generator and is supplied to the selected decode line, is insufficiently high. As a consequence, the dynamic characteristic of the memory system is degraded.